Features of the present application are based on C. Merckling & al. Microelectronic Engineering 84 (2007) 2243-2246 and C. Merckling & al. Appl. Phys. Lett. 89 (2006), the contents of which are hereby incorporated by reference in their entirety.
A traditional metal-oxide-semiconductor (MOS) structure is obtained by depositing a layer of silicon dioxide (SiO2) and a layer of metal on top of a semiconductor die. As the silicon dioxide is a dielectric material its structure is equivalent to a planar capacitor, with one of the electrodes replaced by a semiconductor.
When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor.
A metal-oxide-semiconductor field-effect transistor (MOSFET) includes two terminals, a source and a drain, each connected to separate highly doped regions. These regions can be either P or N type, but they must both be of the same type. These two regions are separated by a not highly doped region known as the body. The body is of a type different than the one of the said two regions. The MOSFET also includes an electrode called a gate, which is located above the body and insulated from all of the other regions by an oxide, usually SiO2.
Smaller MOSFETs are desirable for several reasons. First, smaller MOSFETs may allow more current to pass, due to their shorter length dimension. Second, smaller MOSFETs have smaller gate areas, and thus lower gate capacitance. A third reason for MOSFET scaling is reduced area, leading to reduced cost. Smaller MOSFETs can be packed more densely, resulting in either smaller chips or chips with more computing power in the same area. Since fabrication costs for a semiconductor wafer are relatively fixed, the cost per integrated circuits is mainly related to the number of chips that can be produced per wafer.
Producing MOSFETs with channel lengths smaller than a micrometer is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology.
The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and also to reduce subthreshold leakage when the transistor is off. However, with current gate oxides having a thickness of around 1.2 nm the quantum mechanical phenomenon of electron tunneling occurs between the gate and channel, leading to increased power consumption.
Therefore there is a need for material to replace SiO2.
High-k oxides are good candidates to replace SiO2 as the gate oxide in the future generations of MOSFET devices.
A prior art approach is based on the use of an amorphous high-k oxide layer directly on the crystalline Si substrate. However, epitaxial oxides have superior potential properties because they allow obtaining abrupt oxide-silicon interfaces.
Epitaxial growth of several rare-earth binary oxides and of SrTiO3 has already been demonstrated.
However, these oxides have to be grown at relatively low temperatures between 500° C. and 650° C. and under relatively low oxygen pressures lower than 10−8 Torr to avoid interfacial reactions leading to the formation of SiO2, silicates, or silicides. In addition, the final oxide/Si structures are not stable enough to be compatible with the thermal budget expected for integration in future generation CMOS devices.
Thus, the present invention seeks to find a method for replacing SiO2 for the gate oxide that would mitigate these drawbacks.